1. general description the 74hc4075-q100; 74hct4075-q100 is a trip le 3-input or gate. inputs include clamp diodes. this enables the use of current limiting resistors to interface inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? complies with jedec standard jesd7a ? input levels: ? for 74hc4075-q100: cmos level ? for 74hct4075-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74hc4075-q100; 74hct4075-q100 triple 3-input or gate rev. 1 ? 22 may 2013 product data sheet table 1. ordering information type number package temperature range name description version 74hc4075d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct4075d-q100 74hc4075pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74HCT4075PW-Q100
74hc_hct4075_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 22 may 2013 2 of 13 nxp semiconductors 74hc4075-q100; 74hct4075-q100 triple 3-input or gate 4. functional diagram 5. pinning information 5.1 pinning 5.2 pin description fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) d d d $ % < & $ % < & $ % < & d d d ? ? ? d d d $ % < & fig 4. pin configuration so14 fig 5. pin configuration tssop14 d d d $ % $ % & < * 1 ' 9 & |